Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices. Other examples of thin polished plates may include magnetic disc substrates, gauge blocks and the like. While the technique described here refers mainly to wafers, it is to be understood that the technique also is applicable to other types of polished plates as well. The term wafer and the term thin polished plate may be used interchangeably in the present disclosure.
Fabricating semiconductor devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes. Metrology processes are used at various steps during the semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. One of the characteristics being monitored and controlled is the overlay error. An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. Overlay error is the misalignment between any of the patterns used at different stages of the semiconductor fabrication processes.
When overlay errors are observed, an overlay measurement may be used to apply corrections and to keep overlay errors within desired limits. For example, overlay measurements may be fed into an analysis routine that calculates scanner corrections, referred to as “correctables”, as well as other statistics, which may be used by an operator in order to better align the lithography tool used in the process.
It is noted that one of the error sources affecting the overlay accuracy is wafer geometry. For instance, distortions may occur during fabrication, where chucking of substrates with wafer shape and thickness variations may result in elastic deformation of the wafer that can cause in-plane distortions (IPD). IPD may lead to overlay errors. Therefore, providing the ability to measure and/or predict such wafer geometry induced overlay errors is a vital part of the semiconductor manufacturing process.